A Flash Time-to-Digital Converter with Two Independent Time Coding Lines
نویسندگان
چکیده
Abstrac t-We present a time-to-digital converter with a virtual time coding line created as an equivalent of two independent time coding lines operating simultaneously. Proposed solution allows to overcome the technology limitation in achievable resolution and improve the precision of conversion. The new coding line used in the interpolating time counter designed in an FPGA CMOS device provides the precision (standard deviation) below 35 ps within a 1 s measurement range.
منابع مشابه
Design and Implementation of Offset Error Cancelling Using High Speed Flash Adc
The performance of Flash Analogto-Digital converter is greatly influenced by the choice of Comparator and Thermometer-toBinary encoder design. The work describes the design and pre-simulation of a , 3bit and an 4bit analog to digital converter for low power CMOS. It requires 2-1 comparators, an encoder to convert thermometer code to binary code. The design is simulated in cadence environment us...
متن کاملDigital Controller Designbased on Time Domain for DC-DC Buck Converter
In this paper, the digital controller design for compensating the dc-dc buck converter output voltage has been analyzed in the digital domain. The main idea of this paper is patterning the samples of high order ideal controller and using integral square error in determining digital PID coefficients. This approach provides higher precision of digital controller design and eliminates the need for...
متن کاملUnified Pulsed Laser Range Finder and Velocimeter using Ultra-Fast Time-To-Digital Converter
In this paper, we present a high accuracy laser range finder and velocimeter using ultra-fast time-to-digital converter (TDC). The system operation is based on the measuring the round-trip time of a narrow laser pulse. A low-dark current high-speed PIN photodiode is used to detect the triggered laser beam and to produce start signal. The pulsed laser diode generates 45W optical power at 30ns du...
متن کاملWp 2.4: a 12b 5msl.s Two-step Cmos Aid Converter*
The ADC architecture and timing diagram are shown in Figure 1. The converter consists of a 7b coarse flash stage, a 7b digital-to-analog converter (DAC), a subtractor. and a 6b fine flash stage. One-of-n decoders and ROhIs are used to convert the thermometer code outputs ofthe two flash stages to binarydata, that is thencorrecteddigitally to produce the final output. One bit ofredundancy. or ov...
متن کاملStability Analysis of a Matrix Converter Drive: Effects of Input Filter Type and the Voltage Fed to the Modulation Algorithm
The matrix converter instability can cause a substantial distortion in the input currents and voltages which leads to the malfunction of the converter. This paper deals with the effects of input filter type, grid inductance, voltage fed to the modulation algorithm and the synchronous rotating digital filter time constant on the stability and performance of the matrix converter. The studies are ...
متن کامل